发明名称 MEMORY CIRCUIT
摘要 PURPOSE:To avoid the malfunction of a difference voltage detecting circuit which serves as an amplifying circuit or a reading circuit for memory cell information on a dynamic random access memory by increasing the difference voltage which is supplied to a sense amplifier. CONSTITUTION:A flip-flop circuit consisting of the 1st and 2nd FETQ4 and Q5 is provided together with the 3rd and 4th FETQ11 and Q8 or FETQ12 and Q11 which are driven by the 1st clock signal phi3 or phi3', the 5th FETQ10 or Q9, and control FETQ13 and Q14. For such a memory circuit, the gate-source voltage of the FETQ10(Q9) is controlled by the difference between potentials BL(1) and BL(0) of a bit line and therefore the bit line BL is connected to the FETQ10 (Q9) via the FETQ11(Q12). In such a constitution, the gate voltage of the FETQ10 is controlled by the potential of the line BL to control the capacity of the FETQ10. As a result, the difference voltage of a sense amplifier can be increased and therefore the malfunction can be decreased. Thus it is possible to obtain a memory circuit which can cope with the significant increment of the capacity as well as the high speed of an RAM.
申请公布号 JPS6018891(A) 申请公布日期 1985.01.30
申请号 JP19830126708 申请日期 1983.07.12
申请人 NIPPON DENKI KK 发明人 FUKUZOU YUKIO
分类号 G11C11/419;G11C11/34;G11C11/409;(IPC1-7):G11C11/34;G11C7/06 主分类号 G11C11/419
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