| 摘要 |
PURPOSE:To improve the compactibility and designing property of an IC chip by taking out zero state as level signal with a simple circuit in a desired divider composed of a binary counter. CONSTITUTION:When 60sec detection signal PR is outputted, FFs 8a-8f are reset while being fed to the setting side input of a zero detection circuit 9 to turn a zero detection signal PZ to the ''H'' level. An FF7b lof a zero-returning switch circuit 7 is reset and a control signal PC of the ''H'' level is outputted from an inversion output terminal. A switching circuit 3 selects a 1Hz signal of a frequency dividing circuit 2 again and starts it by switching. The rising of the 1Hz signal is fed to a waveform shaping circuit 4 so that the zero detection signal PZ from the zero detection circuit 9 maintains the ''H'' level thereof until a motor driving signal PD is outputted. In other words, the zero detection signal PZ is outputted only while the contents of FFs 8a-8f of a detection circuit 8 change from ''0'' to ''1'' as the second hand moves to the position of 1sec from the zero position. Thus, the zero state of a divider can be taken out as a level signal with a simple circuit. |
