| 摘要 |
<p>PURPOSE:To avoid blocking even if plural packets arrive simultaneously to one and same outgoing line by applying time division multiplex to a packet arrived to an incoming line by means of a packet multiplex means and leading the result to an outgoing line. CONSTITUTION:A packet from the incoming line is fed to a packet multiplex circuit 34 and a header section multiplex circuit 33 via serial/parallel conversion circuits 32a-32n. The multiplex circuit 34 applies time division multiplex to signals A, B and C as a signal E and the multiplex circuit 3 applies time division multiplex to only the header part as a signal D. The output of the multiplex circuit 34 is written in FIFO memories 35a-35n provided corresponding to each outgoing line by the output of header part decode circuits 36a-36n provided corresponding to the outgoing line of the multiplex circuit 33. Thus, the packet of the header 1 is written in a memory 35a, the packet of the header 2 is written in a memory 35b, and the packet of the header N is written in a memory 35n and they are outputted sequentially to the outgoing line 2.</p> |
