| 摘要 |
PURPOSE:To process simultaneously calculation of the operand address, etc. for 2 operands or above, by cutting out the object instruction in accordance with the instruction length and constituting the instruction at a time so that the instruction can be preserved at the instruction register. CONSTITUTION:The object instruction can be cut out in accordance with the instruction length and at a time this instruction can be preserved at the instruction register. For example, the object instruction is cut out by an instruction cut- out circuit 102 from an instruction buffer 101 in accordance with the instruction length and the instruction is preserved at an instruction register 103. Next, the base register value designated by the B1 portion and B2 portion of the instruction register 103 is read out through signal lines 200 to 203 from a general register 104, is inputted to an adder 105 and an adder 108 respectively and the output of the D1 portion and D2 portion is inputted through signal lines 204 to 205 to the adder 105 and adder 108 respectively. And, the address is calculated by the input data with the adder 105, etc., and is inputted through a memory device 106, etc., to an operator 107. |
