发明名称 |
Method of integrating MOS devices of double and single gate structure |
摘要 |
A nonvolatile semiconductor memory device is provided having a MOS transistor and a floating gate type MOS transistor. The length of an overlap between a floating gate and a drain region of the floating gate type MOS transistor is made smaller than that of an overlap between the gate and the drain region of the MOS transistor.
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申请公布号 |
US4495693(A) |
申请公布日期 |
1985.01.29 |
申请号 |
US19830487765 |
申请日期 |
1983.04.22 |
申请人 |
TOKYO SHIBAURA DENKI KABUSHIKI KAISHA |
发明人 |
IWAHASHI, HIROSHI;ASANO, MASAMICHI;YOSKIKAWA, KUNIYOSHI;MITO, MASAZI |
分类号 |
H01L21/8247;H01L27/088;H01L27/10;H01L27/105;H01L29/423;H01L29/788;H01L29/792;(IPC1-7):G11C11/40 |
主分类号 |
H01L21/8247 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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