发明名称 DATA TRANSFER CONTROL CIRCUIT
摘要 PURPOSE:To perform efficient data transfer without conciousness of an opposite device and queuing by providing a data transfer control circuit capable of controlling independently input/output. CONSTITUTION:A first-in first-out (FIFO) memory 100 capable of independently controlling input/output, is provided on the input side. In addition, an FIFO300, capable of independently controlling input/output, is provided on the output side. A main memory 200 for temporary storage of transferred data is provided between the FIFO100 and FIFO300. A selector 700 selects a read address or write address from address counters 500 and 600, and supplies the address to the main memory 200. A write control 400 fetches data from the FIFO100 on the input side and controls writing into the main memory 200. A write control 900 reads data from the main memory 200, and controls writing into the FIFO300 on the output side.
申请公布号 JPS6017552(A) 申请公布日期 1985.01.29
申请号 JP19830125794 申请日期 1983.07.11
申请人 NIPPON DENKI KK 发明人 KOSHIMIZU YATORI
分类号 H04L13/08;G06F5/06;G06F5/10;G06F5/12;G06F13/00;G06F13/42;(IPC1-7):G06F13/00;H04L13/00 主分类号 H04L13/08
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