| 摘要 |
PURPOSE:To obtain a characteristic as designed by driving a shift register having M-tap by a clock having a frequency being N-times that of an input signal and reading an ROM with a tap output at the interval of (N-1) and adding the read results so as to omit a phase shift circuit and an analog adder circuit. CONSTITUTION:A clock having a frequency four times that of an input data at a signal input terminal 2 is applied to a terminal 10 and one input data is stored in four registers. Thus, an address input of each ROM is changed by the input speed of the data and the operating speed of the ROM can be as much as the speed of the input data. A signal shifted by 1/4 period of the input data is inputted sequentially to ROMs 6a-6d and a sampled value at each 1/4 period of the input data having a desired impulse response stored in each ROM is read. This is added by a full adder 12, converted into an analog signal at a DA converter 7 and outputted though a low pass filter 9. |
