| 摘要 |
PURPOSE:To improve the debug processing efficiency for a specific module having plural lower modules by omitting the debug of lower modules and attaining the debug of only upper modules. CONSTITUTION:When a specific module of a program to be tested is debugged, the set address of a call instruction for lower modules is registered to a bit map memory 5. While the set address of a return instruction to upper modules is registered to a bit map memory 6. Then a real device 1 is operated and a real device CPU4 executes an address instruction coincident with the register data. Thus a reversible counter 9 is counted up and down when said address instruction is equal to a call instruction and to a return instruction respectively. In such a way, the operation of the CPU4 is stopped when the counter 9 is reset to its start point and switched to a CPU14 for execution of debug processing. With use of such a means, the debug is omitted for lower modules. This improves the debug processing efficiency. |
