发明名称 MULTIPLYING CIRCUIT FOR DIGITAL SIGNAL
摘要 PURPOSE:To prevent the accumulation of errors of many multiplying circuits by detecting the maximum value of the control signal which controls the gain of a digital signal and adding the minimum until 1 to the output signal of a multiplier for output. CONSTITUTION:A digital signal is supplied from a terminal 1, and a gain control signal is supplied from a terminal 2. When both signals are set at the maximum value FF (hexadecimal), a detector 4 detects the maximum value FF of the control signal and supplies a high level to a switch 7. The switch 7 selects and delivers 1. For an adder 5, the multiplication result (FFXFF=FE01) of a multiplier 3 needs 16 bits and 01 is defined as an error as long as the result of multiplication is defined s 8 bits. However 1 is added to the FF of the multiplication result and therefore the FF is delivered. As a result, no addition is carried out with accumulation of errors for a multiplying circuit having its control input set at maximum 1 despite a multi-stage connection of such multiplying circuits.
申请公布号 JPS6014327(A) 申请公布日期 1985.01.24
申请号 JP19830120226 申请日期 1983.07.04
申请人 NIPPON DENKI KK 发明人 MUNESAWA ICHIJI
分类号 G06F7/499;G06F7/507;G06F7/52;G06F7/53;H04N5/20;(IPC1-7):G06F7/52 主分类号 G06F7/499
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