发明名称 ERROR DETECTING SYSTEM
摘要 PURPOSE:To detect an error in a correct way even though a continuous 2-bit error is contained in a bit assigned to a parity by extracting the contents latched by a latch means at every (n) units to perform a parity check. CONSTITUTION:The output of a PROM6 is once latched by a latch circuit 7 and then supplied to a microprogram executing circuit 8 to produce an address which gives an access to a next microinstruction. This address is sent to the PROM6 through a bus (a). While the output of the circuit 7 is supplied to an error detecting circuit 9. The circuit 9 detects the error based on a parity check matrix. This parity check matrix is constituted as shown by an equation I in such a case where the microinstruction shows 5. Therefore the error can be detected although the continuous two bits are detective since conditions are satisfied with the parities 1P and 2P.
申请公布号 JPS6014346(A) 申请公布日期 1985.01.24
申请号 JP19830121098 申请日期 1983.07.05
申请人 FUJI XEROX KK 发明人 KINOSHITA HARUNOBU
分类号 G06F11/10;H03M13/13 主分类号 G06F11/10
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