| 摘要 |
PURPOSE:To remove an error output to OFF, generated owing to common timing T between FFs, by delaying signal T to each FF when the output of merging circuit supplied with the content of IFF is checked by OFF. CONSTITUTION:Timing generating circuit 11 generates several timing signals 14- 14' differing in phase, which are supplied to timing distribution circuits 12-12' corresponding to logic units 13-13', and consequently timing distribution circuits 12-12' amplify timing signals of respective phase and then supplies them to logic units 13-13'. Timing distribution circuits 12-12' are provided with several timing supply-suppression control methods, with can control independently several timing signals distributed into logic units 13-13', e.g. those supplied to input FF and output FF. |
