| 摘要 |
PURPOSE:To reduce a through current, to save power consumption and to prevent a latch-up and the incorrect selection of an address decoder by forming an address signal changing steeply to accelerate the amplification of an address buffer or detecting the transition period of an output signal from an address buffer to inhibit transmission. CONSTITUTION:A latch circuit FF is obtained by connecting so as to cross between the input and output of two inverter circuits constituted of n channel MOSFET Q20 (Q22) and p channel MOSFET Q21 (Q23) and its I/O terminals are connected to the input terminal and output terminal of an inverter IV3 respectively. When the input signal and output signal of the IV3 reach a level inverting the latch circuit FF receiving the input and output signals, the latch circuit FF responds the inversion steeply by its forward feedback operation and transmits the inversion to the input and output side of the IV3, so that an address signal formed by the IV3 can be steeply changed. Since the conductance characteristic of the MOSFET is easily inverted in accordance with the output of the IV3, the value is set up to a comparatively small value. |
