发明名称 BIT INTEGRATION CIRCUIT
摘要 PURPOSE:To set the mean voltage of output at zero with a prescribed level of output amplitude and at the same time to facilitate the easy integration for a bit integration circuit, by applying the electric charge stored to a capacitor to the input terminal of an arithmetic amplifier via a switch group. CONSTITUTION:The mean voltage of an output terminal 21 is set at 0V and a swtich 19 is kept off. Under such conditions, the output V21 of an integrated circuit is equal to the sum of the one-sample preceding output and the value obtained by multiplying the electric field of an input terminal 8 by C2/C1. Therefore it is understood that the signal of the terminal 21 is equal to the sum of input signals of the terminal 8. The output voltage is forcibly set at 0V every bit by discharging the electric charge of a capacitor 17 by means of the switch 19. In such a way, a bit integration circuit is obtained. Then the clock of the terminal 8 is set at ''0'' and set in a state as shown in the figure. In such a case, the electric charge stored to the capacitor C2 is totally shifted to the capacitor C1 since the input terminal of an operational amplifier 18 is virtually grounded. In other words, no electric charge remains at stray capacitances C5 and C6.
申请公布号 JPS6011971(A) 申请公布日期 1985.01.22
申请号 JP19830119711 申请日期 1983.06.30
申请人 MATSUSHITA DENKI SANGYO KK 发明人 HONMA KOUICHI;SATOU YOSHIO
分类号 H03M3/02;G06G7/164;G06G7/186;(IPC1-7):G06G7/164 主分类号 H03M3/02
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