发明名称 DATA PROCESSING SYSTEM
摘要 PURPOSE:To increase the resistance of a data processing system to a hit of power supply, the surge voltage, etc. by providing an RAM to store parity bits, and reding and checking the corresponding parity bit in a data reading mode. CONSTITUTION:When the data on a program, etc. is written to an incorporated RAM2, the parity bit corresponding to the data is produced by a parity bit producing circuit 6 on the basis of the data supplied to the RAM2. Then the parity bit is written to an RAM7 for parity bit. When the data is read out of the RAM2, the parity bit related to the data is also read out of the RAM7. At the same time, a parity bit is newly produced and compared with the parity bit which is read out of the RAM7. Then an interruption signal is outputted when the discordance is detected from said comparison. Then a data processing system is reset to its initial state.
申请公布号 JPS6011949(A) 申请公布日期 1985.01.22
申请号 JP19830118304 申请日期 1983.07.01
申请人 HITACHI SEISAKUSHO KK 发明人 KAWAMURA MASAMI;IWATA KATSUMI;FUNATSU KENZOU
分类号 G06F11/10;G06F12/16 主分类号 G06F11/10
代理机构 代理人
主权项
地址