| 摘要 |
Disclosed is an integrated transistor structure having increased conductance and operating speed including a complementary insulated gate field-effect transistor pair, each transistor including a source region and drain region with a gate contact positioned therebetween, ohmic contacts to the source and drain regions, and a diode junction contact to each of the drain regions. The gates of the two transistors are interconnected and function as the input terminal, and the two diode junction contacts are interconnected as the output of the device. The operation of the device is such that the lightly-doped drain regions act as bases of bipolar transistors, with the emitters formed by the p-n junction diodes. The transconductors of the MOS transistors is multiplied by the beta of the bipolar transistors. The ohmic contacts to the drain regions can be interconnected, and the low on resistance of the opposite polarity drive transistor extracts any excess stored charge in the drain region. Two clocked transistors interconnect the complementary insulated gate field-effect transistor pair to voltage potentials whereby operation of the integrated transistor structure is clocked.
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