发明名称 MEMORY CIRCUIT
摘要 PURPOSE:To improve the efficiency of reading/writing information for a memory circuit of a display device or a printer device by reading and writing simultaneously not only the information arrayed in the row and column directions but the information set in a planar direction. CONSTITUTION:The signals S0, S1, A0 and A1 sent from a mode address selection means 1 are supplied to an ROM5. The ROM5 delivers array conversion signals M00, M01-M31. This conversion signal contains 2 bits and shown the positions on an information map where output information D0-D3 given from memory chips M0-M3 exist respectively. Such information D0-D3 and signals M00-M31 are supplied to four multiplexers 6a-6d respectively. Then the read information D0-D3 corresponding to the array on the information map is delivered from multiplexers 6a-6d. In this case, the ROM5 and the multiplexers 6a-6d convert the information arrays given from chips M0-M3 into the information array of the information map.
申请公布号 JPS6010485(A) 申请公布日期 1985.01.19
申请号 JP19830117405 申请日期 1983.06.29
申请人 FUJITSU KK 发明人 ITOU SUMIO
分类号 G09G5/00;G06F12/06;G06T1/60;G11C8/00;G11C11/401;(IPC1-7):G11C8/00;G06F12/02;G09G1/00;G06F15/62 主分类号 G09G5/00
代理机构 代理人
主权项
地址