发明名称 STACK MEMORY CONTROL SYSTEM
摘要 PURPOSE:To write or read data at a high speed by using a means which holds temporarily the writing address together with at least >=2 stack pointers and changing the value of the stack pointer in parallel with the writing and reading operations. CONSTITUTION:When data is written to an address (k) shown by a stack top pointer, the data showing the address (k) stored in a register is supplied to a latch L via a multiplexer P within a period in a machine cycle of a CPU. Then the data of a writing register Rw is written to the address stored in a latch L in a period within the following machine cycle of the CPU and in parallel with a fact that the values of pointers in registers R1-R3 receive +1 respectively. Thus the period is reduced compared with the conventional system for replacement of the pointer values of registers R1-R3. In the same way, the data stored in the address (k) can be read out to a register RR within a machine cycle of the CPU.
申请公布号 JPS6010483(A) 申请公布日期 1985.01.19
申请号 JP19830117325 申请日期 1983.06.29
申请人 FUJITSU KK 发明人 SHINAGAWA AKIO
分类号 G06F9/34;G11C7/00;(IPC1-7):G11C7/00 主分类号 G06F9/34
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