| 摘要 |
PURPOSE:To attain the execution of memory control in response to a system by designing that the memory access control of the cycle steal system by plural devices and the memory access control occupied in one device are both used. CONSTITUTION:A CPU1 issues designation information and a load command to a command register 22 from the CPU1 by using an address/data bus 5 and a control signal 25 at the operation of system. A control command decoder 21 decodes the command on the address/data bus 5 to decode a load signal to the command register 22 and load the designation information on the data bus to the command register 22. When both b0, b1 are logical ''1'', the command register 22 starts a multi-access priority decision circuit 23 via a control bus 27, selects only one in memory access request signals ACS1-n transmitted from plural devices to make one of corresponding ready signals RDY1-n into effective [1]. A memory access timing generating circuit 24 is started at the same time to generate an R/W signal. |
