| 摘要 |
PURPOSE:To test surely a system clock system with one pattern by controlling the data input to ''0'' or ''1'' from the external in a logic circuit where many state storage circuits are constituted into a shift register chain and scan in/out of test data is possible. CONSTITUTION:If a control signal CNTL is set to ''1'' in the test mode, inputs D' of all F/Fs are ''0''. In the normal mode, signals equivalent to inputs D are inputted to inputs D' because the signal CNTL is set to ''0''. In the test mode, all F/Fs are operated as a shift register, and a test clock TC is inputted to write ''1'' from a scan input terminal SI, and all outputs Q are set to ''1''. In this state, inputs D' of all F/Fs are ''0'', and outputs Q of them are ''1''. Then, the mode is switched to the normal mode (the signal CNTL is set to ''1'' still), and a system clock C is inputted to push inputs D' to outpus Q. At this time, if the clock C is supplied normally to each F/F and the F/F itself is operated normally, ''1''s written by scan in are changed to ''0''s. Next, the mode is switched to the test mode again to scan out outputs Q of all F/Fs, and it is checked whether they are all ''0'' or not. |
