发明名称 SQUELCH CIRCUIT
摘要 A squelch circuit in which a phase locked loop (PLL) (5) having a voltage controlled oscillator (VCO) (7) and a phase comparator (10) is used to detect the number of zero crossings, these being low for a speech signal and high for noise. The error voltage produced in the phase locked loop (5) is fed through a network (12) which ensures that the matching of the input signal to the oscillator is faster when the input frequency drops than when the input frequency rises. The input signal is clipped to enhance the frequency spectra of speech by using a limiting amplifier. The muting gate (2) output is derived from the VCO (7) control voltage of the PLL (5) to mute the output of the receiver when the VCO (7) output frequency is higher than a pre-set frequency for more than a pre-set time.
申请公布号 WO8500256(A1) 申请公布日期 1985.01.17
申请号 WO1984AU00112 申请日期 1984.06.21
申请人 THE COMMONWEALTH OF AUSTRALIA 发明人 NOTT, HENRY, ALAN
分类号 H03G3/34;H04B1/10;(IPC1-7):H03G3/20;H03L7/08;H03G3/26 主分类号 H03G3/34
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