Input signal level converter for an integrated CMOS digital circuit

摘要

The level circuit according to the invention consists of the series circuit of a p-channel MOS field-effect transistor comprising two n-channel MOS field-effect transistors, the p-channel MOS transistor being connected with its drain to the terminal with a supply potential Vcc and one n-channel MOS transistor being connected with its source to the terminal for the reference potential Vss. A further n-channel MOS field-effect transistor is connected with its source to a node between the two first n-channel transistors, with its gate to a node between the p-channel transistor and the n-channel transistor of the series circuit immediately connected to it. This node also forms the signal output of the level converter. The signal input is given by the gate of the two n-channel transistors forming, together with the p-channel transistor, the said series circuit, the gate of the p-channel transistor being either also connected to the signal input or being connected to the terminal for the reference potential. The level circuit has the advantage of a high gain and can be dimensioned in such a manner that the occurrence of transverse currents is eliminated in normal operation. <IMAGE>