| 摘要 |
PURPOSE:To enable a self test to be performed for an integrated circuit where a test according to a general random pattern is not valid by incorporating a small-scale circuit which generates a weighted random pattern in a test for a semiconductor integrated circuit. CONSTITUTION:By adding weight bit generation parts 131-135 which are constituted of a plurality of logic gates to an output of a simulated random pattern generation part 103, a weighted random pattern according to a circuit 102 to be tested is generated. Also, a register 105 for controlling weight is connected to the weight bit generation part and is connected to a shift register of the random pattern generation part 103, thus enabling a weight of the random pattern which is generated to be set and changed without providing any special external input. |
