发明名称 DISPLAY CIRCUIT
摘要 PURPOSE:To improve noise resistivity by forming a window signal being logical ''1'' only for a period when a normal vertical synchronizing pulse Pv is obtained in a display circuit for tele-text or the like and gating the vertical synchronizing pulse Pv having a noise pulse Np by this window signal to apply only the normal vertical synchronizing pulse Pv to the counter. CONSTITUTION:When no noise pulse Np is mixed in the pulse Pv, a counter 21 counts a pulse Qh and also is reset by the pulse Pv, then the count value of the counter 21 repeats 262-count after being started ''0'' at point of time of the pulse Pv. If the noise pulse Np is mixed in the pulse Pv, since the counter 21 is reset by this noise pulse Np, the count value of the counter 21 does not reach 262 at the presence of noise pulse Np. Thus, the noise pulse Np is blocked at an AND circuit 25 and only a pulse Q25 corresponding to the pulse Pv is obtained from the AND circuit 25.
申请公布号 JPS607281(A) 申请公布日期 1985.01.16
申请号 JP19830114957 申请日期 1983.06.24
申请人 SONY KK 发明人 YABE TOYOJI
分类号 H04N5/907;H04N7/025;H04N7/03;H04N7/035;H04N7/08;H04N7/081;(IPC1-7):H04N7/08 主分类号 H04N5/907
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