| 摘要 |
PURPOSE:To provide the titled device with an extremely wide pitch control range by forming a phase locked circuit changing its center frequency synchronously with the change of output frequency of a reference oscillator. CONSTITUTION:An output from a loop filter (LF)2 is inputted to a bias adder (ADD)9 and an output from the ADD9 is used as a control voltage of a VCO3. A voltage proportional to the output frequency of a reference frequency oscillator (OSC)8, i.e. a voltage obtained by converting the frequency of a reference clock (d) into voltage, can be applied to the other input of the ADD9. The sensitivity of the bias voltage to the OSC8 is made equal to the control voltage/output frequency sensitivity of the VCO3 to attain pitch control in a wide range. The pitch control range can be changed optionally except limitation due to other factors. Thus, the clock extracting ability of a PLL can be secured and the pitch control is attained in the wide range. |
