发明名称 Masterslice semiconductor device.
摘要 <p>A masterslice semiconductor device has two kinds of basic cells; a first kind (BC1, BC2) having a size the same as that of ordinary basic cells in a previous masterslice semiconductor device and a second kind (BCL) having a size larger than that of the first kind. A number of the large sized basic cells are arranged in columns of a semiconductor substrate to constitute a plurality of basic cells arrays (BLL) which separated in the row direction of the semiconductor substrate. Each of the basic cell arrays (BLL) comprised of basic cells of the second kind (BCL) is situated between two adjacent basic cell arrays (BL,, BL2) comprised of basic cells of the first kind (BC,, BC,). Each region occupied by a basic cell arrays (BLL) of basic cells of the second kind (BCL) can be used for distributing interconnecting lines as in the previous masterslice semiconductor device. At least one basic cell of the second kind (BCL) in each such region serves to interconnect basic cells of the first kind (BC1, BC2) in adjacent basic cell arrays (BL,, BL2) and also serves to constitute an elementary circuit block, a unit cell (UC), in conjunction with basic cells of the first kind.</p>
申请公布号 EP0131464(A2) 申请公布日期 1985.01.16
申请号 EP19840304669 申请日期 1984.07.09
申请人 FUJITSU LIMITED 发明人 SATO, SHINJI C/O FUJITSU LIMITED
分类号 H01L27/092;H01L21/82;H01L21/8238;H01L27/118;(IPC1-7):H01L27/02 主分类号 H01L27/092
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