| 摘要 |
<p>A constraint application processor (10, 30) is arranged to apply a linear constraint to signals from antennas (14). A main antenna aignal is fed to constraint element multipliers (22) and thence to respective adders (16) for subtraction from subsidiary antenna signals. Delay units (15) delay the subsidiary signals by one clock cycle prior to subtraction. The main signal is also fed via a one-cycle delay unit (17) to a multiplier (18) for amplification by a gain factor. Main and subsidiary outputs (24) of the processor (10, 30) may be connected to an output processor (32, 60) for signal minimisation subject to the main gain factor remaining constant. The output processor (32, 60) may be arranged to produce recursive signal residuals in accordance with the Widrow LMS algorithm. This requires a processor (32) arranged to sum main and weighted subsidiary signals, weight factors being derived from preceding data, residual and weight factors. Alternatively, a systolic array (60) of processing cells (61, 62, 63) may be employed.</p> |
