Bit line precharging and equilibrating circuit

摘要

A circuit is described for precharging and equilibrating the bit lines in a semiconductor memory. The circuit includes a pair of precharging transistors, each coupled between its own bit line and a common node, and each adapted to receive a precharging pulse at its gate. A transistor circuit is coupled to the common node to establish thereat a variable operating potential such that when the precharging pulse occurs, one of the precharging transistors conducts to raise its bit line to a precharge potential while simultaneously reducing the operating potential at the common node. The lower voltage at the common node permits the other precharging transistor to conduct so that its bit line is precharged and both bit lines are equilibrated through the conducting transistors.