| 摘要 |
PURPOSE:To enable high density wiring by a method wherein either one of longitudinal wirings or lateral wirings are composed of a plurality of wiring layers, and then wirings belonging to each wiring layer are laid out on the lattice of wirings alternately adjacent to each other, resulting in a multilayer wiring structure. CONSTITUTION:The titled device has a three-layer wiring structure wherein gate metallic wiring layers 17 and low resistant metallic wiring layers 26 of the second layers are assigned as the longitudinal wirings, and wherein the lateral wirings are composed of lateral wirings 18, low resistant metallic wiring layers of the first layers. This structure enables the effective use of gate metallic wirings for the wirings among standard cells. Besides, the wirings 17 and 26 are al ternately placed in the lateral wiring grid, i.e., the grid wherein longitudinal wirings are arranged. Such a manner enables to increase the density in a logic LSI and the speed-up. |
