| 摘要 |
<p>PURPOSE:To lessen the margin of pulse potential for the fluctuation of power voltage by making a power source for DC potential to be applied to the drain of a field effect transistor and a power source for applying a specified bias to the pulse potential to be impressed on the gate, common to each other. CONSTITUTION:A precharging transistor is composed of an enhancement type FET 11 of surface channel operation. When an FET of buried channel operation is used, in contrast to a voltage of Veff=3.75V is required in order to apply phieff=3.0V, the minimum necessary for resetting an FD 2, a gate voltage of Veff=phieff/0.9=3.33V is sufficient in this case. Besides, the dispersion phidev of channel potential can be suppressed to + or -1.0V. Since the fluctuation of power voltage is VPGL=VPD, and both follow each other by using the same power source, it is possible to lessen the margin of Vreset for the fluctuation of the power voltage.</p> |
