发明名称 VIDEO SIGNAL PROCESSING CIRCUIT
摘要 PURPOSE:To perform processing utilizing the horizontal correlativity of video signals without spoiling a vertical interval reference (VIR) signal with a simple constitution, by suitably using two inputs of an arithmetic means as video signals of the same timing. CONSTITUTION:An original carrier chrominance signal supplied to an input terminal 1 is supplied to a changeover switch 14 after it is delayed by means of a 1-horizontal scanning period delaying line 3 or inverted by means of an inversional amplifier 19. The changeover switch 14 is connected to B-terminal only when a VIR signal exists (in the 19th and 282nd horizontal scanning periods T19 and T282) and to A-terminal in the other period, by means of a changeover pulse from a changeover pulse generating circuit 8. As a result, in the periods other than the T19 and T282 the original carrier chrominance signal and 1-H delayed carrier chrominace signal are calculated at a subtractor 2 and a comb line filter for chroma is constituted. Since the original carrier chrominance signal and its iverted signal are calculated during the periods T19 and T282, a signal which is twice as large as the original carrier chrominance signal is obtained from the subtractor 2 and the VIR signal is never spoiled.
申请公布号 JPS604396(A) 申请公布日期 1985.01.10
申请号 JP19830112409 申请日期 1983.06.22
申请人 CANON KK 发明人 SAKATA TSUGIHIDE
分类号 H04N9/64;H04N9/78;(IPC1-7):H04N9/78 主分类号 H04N9/64
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