| 摘要 |
PURPOSE:To fix an input to an optional polarity to improve the difficulty of check data generation and the lowness of fault detection rate by giving the output of a clock width correcting circuit, which is provided in an integrated circuit, with a fixing designation signal from the outside of the integrated circuit. CONSTITUTION:Normally, a high level is inputted as the fixing designation signal to an input terminal 532. When the clock signal inputted to an input buffer circuit 4 is changed from the high level to the low level, one input 601 of an NAND circuit 6 becomes high, and an input 602 becomes low after a certain time delay by a delay circuit 5. Therefore, a pulse having a pulse width equal to the delay time is outputted to the output of the circuit 6. Meanwhile, the fixing designation signal is made low when a fault is detected, and the input 602 is fixed to the high level in this case. Consequently, the output of the circuit 6 becomes high or low when the input of the circuit 4 is made high or low in accordance with the output of the circuit 6, and the circuit is checked in the state where the input passes through to the output as it is, and the generation of check data is made easy. |
