发明名称
摘要 A combinational logic device, such as an AND gate, is connected to control the flow of information along a wordline from the AND plane to the OR plane of a PLA (programmed logic array). To each such combinational logic device is applied an input signal from a source external to the PLA, so that the PLA's output can respond relatively quickly to this input signal-that is, the PLA is capable of relatively quick decision making.
申请公布号 JPS60500039(A) 申请公布日期 1985.01.10
申请号 JP19840500349 申请日期 1983.12.01
申请人 发明人
分类号 G06F9/22;H03K19/177 主分类号 G06F9/22
代理机构 代理人
主权项
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