| 摘要 |
<p>A semiconductor memory device including word lines (WL), bit lines, and memory cells (in MCA1, MCA2) located at each cross point therebetween, wherein each of the word lines (WL) is divided to form segmented word lines (WL1, WL2). Each of the word line segments is driven by an individual private word driver (Qwd1, Qwd2). The individual private word drivers are activated together in response to a word selection signal.</p> |
