发明名称 PHASE LOCKED LOOP CIRCUIT
摘要 PURPOSE:To increase the stability of the operation of a digital circuit section by detecting the difference between a pulse having a pulse width decided by an edge of an input signal and an output clock and a pulse having a pulse width decided by the output clock only. CONSTITUTION:Both leading and trailing edges of an EFM (eight to fouteen modulation) signal being an input signal are detected by an edge detector 9 and become a pulse generating signal (C) of the 1st pulse generator 10, which generates pulses until the next leading edge of an output clock signal. The 2nd pulse generator 11 generates a pulse (D) for one clock's share of an output clock signal (E) succeeding to the output pulse of the generator 10. The output of the generators 10, 11 is inputted to a pulse difference detector 12 to produce a difference signal having a pulse width and this signal is applied to a low-pass filter and a voltage controlled oscillator.
申请公布号 JPS603230(A) 申请公布日期 1985.01.09
申请号 JP19830111211 申请日期 1983.06.20
申请人 MATSUSHITA DENKI SANGYO KK 发明人 KAMEDA KEIICHI
分类号 G11B20/10;H03D13/00;H03L7/08;H03L7/085;H04L7/033 主分类号 G11B20/10
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