Semiconductor memory using multiple level storage structure.

摘要

A semiconductor memory for reading and writing stored charge in an X-Y address system includes a plurality of memory cells each consisting of one capacitance element (116) and one MOS-FET (115) in a matrix. A multiple level storage structure is used for reading and writing data of more than two levels stored in the capacitance elements (116) by applying a multi-level step voltage to the plateelectrode of the capacitance or to the gate electrode of MOS-FET (115).