| 摘要 |
PURPOSE:To offer a phase correcting circuit where a phase among channels is made coincident automatically by using a complete tributary synchronizing clock so as to multiplex lots of the channels. CONSTITUTION:In Fig., 1F1-1F4, and 2F1-2F4 are D flip-flops, AphiC1-AphiC3 are automatic phase controllers, PC1-PC3 are phase comparators, and INV is an inverter. Each channel has a slight phase difference (but the frequency is the same) and in taking a clock of an optional channel, e.g., the clock of the 4th channel as a reference tentatively, an input of the 2nd D flip-flop 2F1 of the 1st channel cannot be obtained correctly. Thus, it is required to give a delay to a data by providing a proper delay circuit between the 1F1 and the 2F1. That is, the clock of the 4th channel and a clock of other channel are compared by the phase comparator PC and the data is obtained correctly by processing a clock as it is and giving a delay to another clock by a half bit. |
