发明名称 |
ROM CAPABLE OF ACCESS FROM X AND Y DIRECTIONS |
摘要 |
<p>PURPOSE:To attain reading of data at the same speed from both X and Y directions by actuating X and Y sense means interlocking X and Y line driving means selected by the address signal and transmitting both high and low logic levels of a memory cell. CONSTITUTION:A memory cell array 1 of (mXn) bits has Q corresponding to each bit. The drain terminal of each Q is connected to a high potential VCC. Then the gate and source terminals are connected to the X and Y lines respectively via a wiring means 11 in response to level ''1'' and the data expected to each bit. While the gate and source terminals are connected to the y and X lines respectively via a wiring means 12 in response to level ''0''. The X and Y lines are reset to ''0'' for each input of the signal impressed to an address decoder and the X and Y selection signals respectively in a readout mode. Then an X line driver 2a and a Y line sense amplifier 3b or a Y line driver 2b and an X line sense amplifier 3a are actuated in response to both X and Y selection signals. Thus each Q output is transmitted through a selection part.</p> |
申请公布号 |
JPS601696(A) |
申请公布日期 |
1985.01.07 |
申请号 |
JP19830108828 |
申请日期 |
1983.06.17 |
申请人 |
FUJITSU KK |
发明人 |
IGARASHI TAKEYOSHI;OKAZAKI SUSUMU;KOBAYASHI KAZUYA |
分类号 |
G06T1/60;G09G5/24;G11C7/00;G11C17/00;G11C17/12;(IPC1-7):G11C17/00;G09G1/00 |
主分类号 |
G06T1/60 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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