| 摘要 |
PURPOSE:To reduce the titled circuit at its size and price by consituting a multiple filter by a multiplier, a coefficient generating circuit and a pair of filters. CONSTITUTION:A complex signal of a receiving video is multiplied by a coefficient generated from a factor generating circuit 2 every bit in accordance with the number N of steps of an MTI circuit every bit. An adder 12 adds a signal sent from the multiplier 1 to a signal sent from a delay circuit 11 and the added signal is delayed again by a transmission period in a delay circuit 11. At the time completing the processing of (N+1) bits, a switch 21 is turned on by a gate pulse, the processed signal is divided by an output from the coefficient generating circuit 2 in a divider 22 and the amplitude of I/O signals is uniformed and outputted. |
