| 摘要 |
PURPOSE:To attain reading of data accurately from an objective address at all times by inhibiting an output of read data to an external part simultaneously with the start of movement of a head executing data reading and detecting the stop of movement of the head to release the output inhibiting state of the reading data. CONSTITUTION:When a direction designating signal DIR and a step signal STP are inputted from a host computer 1, the exciting phase of drive signals phiA, phiB, phiC and phiD supplied from a pulse motor control circuit 2 to a pulse motor 3 is switched, the pulse motor 3 is driven and the head 4 is moved. On the other hand, when the step signal STP is inputted, an output of a timer 11 is inverted to a low level. When the head 4 reaches an objective track position, since the input of the step signal STP from the host computer 1 is stopped, the timer 11 inverts its output from a low level to a high level at prescribed time after the input of the final step signal STP, an AND gate 9 is set and the reading data is outputted to the host computer 1. |
