发明名称 DMA CONTROL SYSTEM
摘要 PURPOSE:To remove the limitation in the mounting position of a channel by making a local burst possible with a system which is not an interlacing mode and, furthermore, without the highest priority. CONSTITUTION:Since a flip flop 15 is actuated and a bus request is outputted, and then, a bus occupancy permit is returned from a CPU when the internal request of a channel is generated, a counter 17 counts the bus occupancy permit. When the counter 17 counts the permit for more than predetermined times, the counter 17 generates an end signal END. When the end signal END is generated, a bus request is processed at the timing when the next bus occupancy permit arrives, but, until the next bus occupancy permit comes, a flip flop 16 outputs a DMA data sequence actuating signal at every occupancy permit passing through a gate 11. By means of the actuating signal, a DMA data transferring sequence is executed by one time to reset the flip flop 16 by means of the DMA sequence end signal.
申请公布号 JPS60557(A) 申请公布日期 1985.01.05
申请号 JP19830108645 申请日期 1983.06.17
申请人 FUJITSU KK 发明人 KAMIDATE MORIHIRO;HASHIMOTO SHIGERU
分类号 G06F13/28;G06F13/372;(IPC1-7):G06F13/28 主分类号 G06F13/28
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