| 摘要 |
PURPOSE:To improve the speed of the buffer memory operation of a computer system provided with a buffer memory function by using two cyclic counters which advances whenever readout and writing are made. CONSTITUTION:When a specified address for writing is designated an address decoder DCR1 detects the address and controls a gate circuit G1 to open it. When a writing control signal W arrives, a pointer WP for writing adds +1 to the content and transmits the added content to a memory RAM. When a specified address for reading out is designated another address decoder DCR2 detects the address and makes control so as to open another gate circuit G2. When a readout control signal R arrives, a pointer RP for reading out adds +1 to the content and transmits the added content to the memory RAM. The data of a memory area between the addresses designated by the pointers WP and RP are held at the memory RAM as effective data. |
