发明名称 MEMORY CONTROL DEVICE
摘要 PURPOSE:To shorten the processing time of a memory control device by obtaining the OR and AND of internal and external data of a memory and rewriting a specified bit only. CONSTITUTION:External data q0-q3 of a memory outputted from a CPU25 are supplied to data input terminals of memories 12-15. If the logical operation is limited to the AND operation and OR operation and when the AND of the external data of a memory and internal data of an address of the memories 12-15 is obtained, data P0-P3 of the bit of the internal data of the memories 12-15 corresponding to the bit which is ''0'' of the external data q0-q3 are rewritten to ''0''. When the OR is obtained, data P0-P1 of the bit of the internal data of the memories 12-15 corresponding to the bit which is ''1'' of the external data q0-q3 are rewritten to ''1''.
申请公布号 JPS60554(A) 申请公布日期 1985.01.05
申请号 JP19830108117 申请日期 1983.06.16
申请人 TOSHIBA KK 发明人 NISHIURA MASAAKI
分类号 G06F12/00;G06F13/16;(IPC1-7):G06F13/16;G06F12/02;G11C7/00 主分类号 G06F12/00
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