| 摘要 |
The invention relates to a parallel multiplier, made as a MOS integrated circuit, operating sequentially with the aid of dynamic-memory elements. The multiplier includes two registers RT and RPS, a device PB for working out low-significance binary elements P0 to PM-1, a device PF for working out high-significance binary elements PM to PM+N-1, and a clock HOR. The first binary element of the mulitplier Y2p = Y0 is multiplied with all the binary elements X0 to XN-1 of the multiplicand. The partial products Xn, Y0 are then supplied to the first series of addition cells SIGMA 00 to SIGMA 0N-1, which supplies the first output binary element P2p=Po. The partial products Xn, Y1 are then formed and supplied to the second series of addition cells SIGMA 10 to SIGMA 1N-1 which accumulates them with the preceding results, present on the output capacitances of the first series of addition cells, and so on by accumulating in one, then the other, of the lines of addition cells. At the end of the cycle, the higher-order binary elements are collected by the second device to form the high-order output. The invention relates to parallel multipliers made as MOS integrated circuits. <IMAGE>
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