发明名称 SCHALTUNGSANORDNUNG ZUR POTENTIALFREIEN ERFASSUNG VON BINAEREN ELEKTRISCHEN SIGNALEN
摘要 1. A circuit arrangement for d. c. -isolated detection of binary electrical signals of different pulse levels by an opto-coupler (7) whose input is connected via a current-limiting resistor (6) to the input terminals (2 and 3) of the circuit arrangement, characterised in that a control circuit (5) is arranged between the input terminals (2 and 3) in series with the input of the opto-coupler (7) and the current-limiting resistor (6) to feed a current into the input of the opto-coupler (7) when actuated ; that a voltage-limiting device (1) arranged between the input terminals (2 and 3) emits signals of standardized level at its output, derived from the binary signals ; that a gate circuit (4) controlled by keying pulses (P) is connected between the output of the voltage-limiting device (1) and the control input of the control circuit (5) to sample the derived signals, and that the output of the opto-coupler (7) is connected to the input of a storage device (9) in which the voltage which occurs at the input of the storage device (9) when the current is fed into the input of the opto-coupler is stored at least for the time between two consecutive keying pulses, and is available at the output of the storage device (5).
申请公布号 DE3322896(A1) 申请公布日期 1985.01.03
申请号 DE19833322896 申请日期 1983.06.23
申请人 SIEMENS AG 发明人 KUEHNE,WOLFGANG
分类号 H03K17/795;H04B10/00;(IPC1-7):G01R19/25;H04L25/20 主分类号 H03K17/795
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