| 摘要 |
<p>A microinstruction control storage mechanism includes a read-only store (ROS), writeable control store (WCS), first cycle control store, and a reserved portion of main storage in a data processing system. As required, blocks of microinstructions are paged into the WCS from the main storage. An array of single-bit storage devices, accessed by microinstruction addresses utilized to access microinstructions from the ROS, signal the existence of a faulty microinstruction from the ROS as determined by maintenance or design personnel. In response to a halt signal from an accessed single-bit storage device, an address substitution mechanism creates a microinstruction address which identifies a main storage location and may have to be used to initiate transfer of a block of microinstructions from main storage to the WCS to provide access to a particular substitute microinstruction for the faulty microinstruction.</p> |
