发明名称 WATCHDOG TIMER CIRCUIT
摘要 <p>PURPOSE:To reduce the probability of generation of malfunction at the time of runaway by monitoring the runaway of software by two decoders. CONSTITUTION:An address is supplied from a microcomputer (MPU) to the address decoders 1, 2 through an address bus. The output of the decoder 1 is connected to the input of a monostable multivibrator 3. A Q-output of the monostable multivibrator 3 is applied to one input of a NAND circuit 5 and the output of the address decoder 2 is supplied to the other input of the NAND circuit 5. The output of the NAND circuit 5 is supplied to the input of a monostable multivibrator 4 and the Q-output of the monostable multivibrator reduced to a signal indicating the generation of an alarm in a watchdog timer circuit.</p>
申请公布号 JPS59229657(A) 申请公布日期 1984.12.24
申请号 JP19830103357 申请日期 1983.06.09
申请人 FUJITSU KK 发明人 SATOU JIYUNICHI;SAKATA TAKAO;YAMAZAKI KIYOHIRO
分类号 G06F11/30;G06F1/14;G06F11/00;(IPC1-7):G06F11/30;G06F1/04 主分类号 G06F11/30
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