发明名称 SEMICONDUCTOR MEMORY
摘要 PURPOSE:To prevent a malfunction of a timing control circuit which is due to the noise produced from an electric power supply line by making use of the action timing signal of a data output buffer to make a edge trigger circuit blind when the actuation is started. CONSTITUTION:An edge detection signal phi is supplied to a timing control circuit TG with variation of an address signal to produce a series of required timing signals. Plural data output buffers are started all at once when a timing signal phiop which starts a data output buffer has the rise in a reading mode. In this case, an edge trigger circuit EG is made blind with a timing signal phidk produced from an AND circuit which receives the signal phiop and a delay signal phiop' of the inverse signal of the signal phiop. Therefore the signal phi is never transmitted to the circuit TG in such a case where a malfunction is produced by the noise of a power supply line due to a fact that plural data output buffers are started all at once.
申请公布号 JPS59229786(A) 申请公布日期 1984.12.24
申请号 JP19830102687 申请日期 1983.06.10
申请人 HITACHI MAIKURO COMPUTER ENGINEERING KK;HITACHI SEISAKUSHO KK 发明人 YOSHIDA MASAHIRO;KEMIZAKI KANEHIDE;MATSUURA NOBUKI;KOYAMA YOSHIHISA;OGATA SHINKOU
分类号 G11C11/41;G11C11/34;G11C11/403;(IPC1-7):G11C11/34 主分类号 G11C11/41
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