发明名称 DEVICE FOR DEVELOPING SYSTEM
摘要 PURPOSE:To form a precise brake signal with a simple constitution by providing the titled device with a memory which is simultaneously selected in accordance with a memory access from a computer system developing the system. CONSTITUTION:The brake memory BM to be simultaneously selected in accordance with a memory access from the computer system developing the system is prepared. The contents of the brake memory BM are successively read out in accordance with the execution of a program. The brake memory BM supplies a brake signal allowing the execution to be continued if the read-out signal is ''0'' or stopping the execution if ''1'' to a brake control circuit BC. Receiving the brake signal, the brake control circuit BC stops the execution of the program in the microprocessor MCU.
申请公布号 JPS59229651(A) 申请公布日期 1984.12.24
申请号 JP19830102571 申请日期 1983.06.10
申请人 HITACHI SEISAKUSHO KK 发明人 OOTA YUUJI
分类号 G06F11/28;G06F11/22 主分类号 G06F11/28
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