发明名称 |
INFORMATION PROCESSOR |
摘要 |
PURPOSE:To expand the development of a program and the supporting function of a test and to provide a function supporting the performance evaluation by trapping a specified I/O device only when the number of accesses of a specific instruction to the specified I/O device exceeds the specified number of times. CONSTITUTION:The I/O device number of an I/O device to be trapped is set up in a trap register TR through an input line I2. The upper limit value of the number of accesses is set up in a counter CNT through an input line I1. In the process of successive execution of a program by a central processor, information for distinguishing the I/O device is entered to an I/O address register through an input line I3. When the contents of the trap register TR coincide with the contents of the trap register TR coincide with the contents of the I/O address register, the counter CNT is subtracted one by one. When the contents of the counter CNT is turned to ''0'', an interruption factor flip flop is turned on and a gate GT is closed.
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申请公布号 |
JPS59229655(A) |
申请公布日期 |
1984.12.24 |
申请号 |
JP19830104130 |
申请日期 |
1983.06.13 |
申请人 |
HITACHI SEISAKUSHO KK;NIPPON DENSHIN DENWA KOSHA;OKI DENKI KOGYO KK;NIPPON DENKI KK;FUJITSU KK |
发明人 |
KIKUCHI SUSUMU;TOKIZAWA IKUO;SHINTANI HIROSHI;MUNAKATA HIDENAO;TOJIYAMA TAKASHI;INOUE AKIRA |
分类号 |
G06F11/28;G06F11/36;(IPC1-7):G06F11/28;G06F9/06 |
主分类号 |
G06F11/28 |
代理机构 |
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代理人 |
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