| 摘要 |
PURPOSE:To avoid inhibition of the memory output in a writing mode and to deliver the memory output as it is by providing an output control circuit into a memory to perform switching between a normal action mode to clamp the memory output in a writing mode and a diagnosis mode to deliver the memory output as it is even in the writing mode. CONSTITUTION:The control input signal DCK applied from outside (a CPU, etc.) is set at a low level in a normal action mode and then a high level in a diagnosis mode respectively. Such signal DCK is applied to an NOT input terminal of an AND circuit 15. Therefore the output of the circuit 15, i.e., an output inhibiting signal VINH is always set at a low level as long as the signal DCK is kept at a high level (diagnosis mode) regardless of the state of the output of an input buffer circuit 14. Thus the memory output is not clamped. While the signal VINH is set at a low level (reading cycle) or a high level (writing cycle) in response to the value of the NOT side of the circuit 14 as long as the signal DCK is kept at a low level (normal action mode).
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